1. Field of the Invention
The present invention relates generally to the field of computer systems and in particular, to translation lookaside buffers as used in memory paging subsystems.
2. Prior Art
Known prior art processors utilize a technique known as paging in order to manage memory resources. Paging is a memory management technique wherein a program is divided into uniform sized blocks called pages. Paging is used in support of various computer system features such as multi-tasking. An example of a processor utilizing paging is the Intel486.TM. family of processors, available from Intel Corporation of Santa Clara, Calif.
In a paging system data is moved to and from system memory by pages. A key aspect of paging is the translation of an address provided by a program, termed a linear address, to a physical address. The physical address is the real address of the page of data in storage. Various computer architectures utilize different address schemes. The address translation scheme as utilized by the Intel486 product is described with reference to FIG. 1. Referring to FIG. 1, a linear address is provided to a paging unit. Note that a linear address 101 is provided to the paging unit when servicing a page fault. A page fault occurs when a page accessed by an executing program, is not in memory. The linear address is first compared to entries in a Translation Lookaside Buffer (TLB) 102. The TLB 102 is a cache of the thirty-two most commonly referenced page table entries of a currently executing task. The page table entries contain the physical address for the page in a storage medium. If the linear address is found, a TLB hit has occurred. Thus the desired physical address is found directly in the TLB. This is desirable since it avoids subsequent processing by the paging unit and results in an increased in speed in the translation of a linear address to physical address.
If the linear address is not found in the TLB 102, then the linear address must be translated. The Intel486 utilizes a two level translation scheme. A first, portion of the linear address is utilized to index to an entry in Page Directory 104. The Page Directory 104 is a table of indices into Page Table 105. In the Intel486 the upper ten bits of the linear address are used as an index to the Page Directory 104.
A second portion of the linear address provides an offset to the Page Table index retrieved from the Page Directory 104 to create an index to one of the Page Table entries. Each Page Table entry in Page Table 105 contains the starting address of the page frame as well as statistical information about the page. This starting address is the desired physical address for the page.
Processing in this manner continues until a task switch occurs. A task switch may occur as a result of the expiration of allotted time for a task, or as a result of an interrupt. In any event, whenever a task switch occurs, the page directory and page table for the new task are loaded, and the TLB must be flushed. By flushed it is meant that the TLB's contents are cleared. The contents of the TLB are entered as page faults occur in the executing task. As tasks are continually swapped in and out, the TLB is continually being flushed. This has the effect of wasting the effort of building entries in the TLB in a prior execution of the task.
Thus, it is desirable to improve utilization of a Translation Lookaside Buffer by eliminating the need to reload the TLB through page faults when a task switch occurs.